Introduction
Ever wondered why chip designers don't always use a full set of PMOS and NMOS transistors in a logic circuit? Sometimes, using fewer transistors — or a smarter arrangement — leads to better results. That's exactly what ratioed logic is all about.
In static CMOS circuit design, there are three main families: complementary CMOS, ratioed logic, and pass transistor logic. This post focuses on ratioed logic — what it is, how its two types work, and why one of them (DCVSL) is specifically designed to kill a sneaky problem called static current flow.
By the end, you will understand:
- What ratioed logic means and why it exists
- How Pseudo NMOS logic simplifies circuit design
- How DCVSL works and why it avoids wasted current
- The role of pull-up and pull-down networks in both types
Table of Contents
- What Is Ratioed Logic?
- Pseudo NMOS Logic
- Why Replace the Pull-Up Network?
- DCVSL — Differential Cascode Voltage Swing Logic
- What Is Static Current Flow?
- How DCVSL Eliminates Static Current
- Key Takeaways
- FAQs
What Is Ratioed Logic?
Ratioed logic is a type of static CMOS circuit where the pull-up and pull-down networks are not perfectly symmetric like in standard complementary CMOS. Instead, one side (usually the pull-up) is simplified or replaced.
Ratioed logic splits into two types:
- Pseudo NMOS Logic
- DCVSL (Differential Cascode Voltage Swing Logic)
Both types use the idea that the PMOS pull-up network and the NMOS pull-down network often implement the same logic function. So why build both? Ratioed logic removes or simplifies one side to save area and complexity.
Pseudo NMOS Logic
The word pseudo means partial or half. In Pseudo NMOS logic, only half of the normal complementary CMOS structure is used.
Here is what happens:
- The pull-down network is a full NMOS transistor network (same as in standard CMOS).
- The pull-up network is replaced by a single load — either a resistor or a transistor that is always ON.
This "always-ON" load transistor acts like a permanent current path from VDD to the output.
Why Use a Transistor Instead of a Resistor?
You might ask — why not just use a plain resistor as the load? The answer is simple:
Fabricating a resistor in CMOS technology is not easy. Resistors take up a lot of chip area and are hard to control precisely. So, a transistor is preferred as the load element.
The load transistor can be:
- An NMOS transistor with its gate connected to VDD
- A PMOS transistor with its gate connected to GND
- A depletion-mode transistor
The key rule: whatever transistor is used as the load must always stay in the saturation region, so it continuously supplies current from VDD to the output node.
How the Output Is Decided
- If the pull-down network is ON → current flows from VDD through the load, then to GND. Output = LOW.
- If the pull-down network is OFF → current flows from VDD to the output. Output = HIGH.
The "ratio" in ratioed logic comes from the sizing ratio between the load and the pull-down transistors — this ratio determines how strong the logic levels are.
Expert Tip: The load transistor in Pseudo NMOS must be sized carefully. If it is too strong relative to the pull-down network, the output LOW level will not reach true logic 0 (GND). This is the main trade-off in ratioed logic.
Why Replace the Pull-Up Network?
In standard complementary CMOS, the PMOS pull-up network and NMOS pull-down network both implement the same logic function — just in dual form. For example, if pull-down implements NAND, pull-up implements NOR, and together they give a correct output.
Since both networks implement the same logical behavior, designers asked: Do we really need both?
Pseudo NMOS says no — replace the pull-up network with a simple always-ON load. This:
- Reduces transistor count
- Simplifies layout
- Saves chip area
The trade-off is that the circuit consumes a small amount of static power when the output is LOW (because the load is always ON and current always flows). This is acceptable in some designs.
DCVSL — Differential Cascode Voltage Swing Logic
DCVSL is the second type of ratioed logic. The full name breaks down like this:
| Term | Meaning |
|---|---|
| Differential | Uses two complementary pull-down networks |
| Cascode | Cross-coupled configuration (different transistor arrangement) |
| Voltage Swing | Output swings the full range from 0 to VDD |
| Logic | It performs digital logic operations |
DCVSL has two pull-down networks — PD1 and PD2 — and two PMOS load transistors — M1 and M2.
The Cross-Coupled Connection
The key trick in DCVSL is cross-coupling:
- The output of PD1 is connected as the gate input of M2.
- The output of PD2 is connected as the gate input of M1.
This creates positive feedback — unlike most amplifier configurations (common source, common drain) which give negative feedback, DCVSL gives positive feedback. This makes switching sharp and fast.
Inputs Are True and Complemented
- PD1 receives inputs in their true form: A, B
- PD2 receives inputs in their complemented form: Ā, B̄
This ensures PD1 and PD2 are never both ON at the same time. When one is ON, the other is OFF — always.
Expert Tip: DCVSL naturally generates both the output Q and its complement Q̄ at the same time. This is useful in logic designs that need both polarities without adding extra inverters.
What Is Static Current Flow?
To understand why DCVSL is useful, you need to know about static current flow — a problem in CMOS circuits.
In a standard CMOS inverter, there is a PMOS transistor (pull-up) and an NMOS transistor (pull-down) connected in series between VDD and GND. During switching, there is a brief moment — Region 3 of CMOS inverter operation — where both PMOS and NMOS are ON at the same time.
When both transistors are ON simultaneously:
\[ I_{static} = \frac{V_{DD}}{R_{PMOS} + R_{NMOS}} \]
There is a direct short-circuit path from VDD to GND. This current is called static current (also known as short-circuit current or crowbar current). It:
- Wastes power
- Generates heat
- Reduces battery life in portable devices
In Pseudo NMOS, this problem exists because the load is always ON. But DCVSL is specifically designed to eliminate this problem.
How DCVSL Eliminates Static Current
Here is how DCVSL avoids static current step by step:
- Suppose the output OUT = 0 (LOW).
- This 0 is fed as the gate input to M2 → M2 turns ON.
- At the same time, since OUT = 0, OUT̄ = 1.
- This 1 is fed as the gate input to M1 → M1 turns OFF.
- Now, M1 is OFF and PD1 is also OFF → no current path from VDD to GND on the left side.
- M2 is ON and PD2 is OFF → again, no complete current path.
The result: M1 and PD1 never turn ON at the same time. M2 and PD2 never turn ON at the same time.
Because of this cross-coupled design, there is no moment when both the pull-up transistor and pull-down network on the same side are ON together. So the short-circuit path from VDD to GND never forms.
No static current = lower power consumption = better energy efficiency.
This is the main advantage of DCVSL over Pseudo NMOS.
Key Takeaways
- Ratioed logic is a static CMOS family where pull-up and pull-down networks are not symmetric.
- Pseudo NMOS replaces the pull-up network with a single always-ON load transistor (resistor or transistor in saturation).
- A transistor is preferred over a resistor as the load because resistors are hard to fabricate in CMOS.
- DCVSL uses two pull-down networks with complementary inputs and cross-coupled PMOS transistors.
- The cross-coupling gives positive feedback and ensures M1/M2 are never ON together.
- DCVSL's main purpose is to eliminate static current flow, saving power.
- DCVSL provides a full voltage swing (0 to VDD) at the output.
Action Steps:
- Draw a Pseudo NMOS inverter and label the load transistor, pull-down network, VDD, and GND.
- Trace the current path in DCVSL for both OUT = 0 and OUT = 1 conditions.
- Review the five operating regions of a CMOS inverter to understand where static current appears.
Next Steps:
- Study pass transistor logic — the third type of static CMOS circuit.
- Explore dynamic CMOS logic (domino logic) for high-speed designs.
- Learn about power dissipation in CMOS: static, dynamic, and short-circuit components.
FAQs
Q1: What does "ratioed" mean in ratioed logic? It refers to the sizing ratio between the always-ON load transistor and the pull-down network transistors. This ratio determines the output voltage levels. If the ratio is wrong, the LOW output may not reach 0V properly.
Q2: Why is the load transistor always kept in the saturation region in Pseudo NMOS? The load transistor must be in saturation to act like a constant current source. This ensures a steady supply of current from VDD to the output, regardless of the pull-down network's state.
Q3: What is the difference between Pseudo NMOS and DCVSL? Pseudo NMOS uses one pull-down network and one always-ON load — simple but has static current when output is LOW. DCVSL uses two complementary pull-down networks with cross-coupled loads, eliminating static current entirely.
Q4: What is static current flow in CMOS? Static current (short-circuit current) flows when both the PMOS pull-up and NMOS pull-down transistors are ON at the same time, creating a direct path from VDD to GND. This wastes power and should be avoided.
Q5: Does DCVSL generate both Q and Q̄ outputs? Yes. Because DCVSL has two pull-down networks with true and complemented inputs, it naturally produces both the output and its complement simultaneously — a useful feature for logic design.
Q6: Is DCVSL faster than standard CMOS? DCVSL can be faster in certain configurations due to its positive feedback (cross-coupling), which sharpens transitions. However, it requires more transistors and careful input complementation, making it more complex to design.
Q7: Can I use DCVSL for any logic function? Yes, as long as you can express the logic function in two complementary pull-down networks (one in true form, one in complemented form). It works for AND, OR, NAND, NOR, XOR, and more.
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